POSITION SUMMARY Responsibilities:
* Participate and Provide inputs for large networking chips Physical Design Methodology
* Work on Blocks with IO, PLL and Efuse macros and take it through complete signoff
* Work on closing final DRCs, manually or with scripts
* Work on AP routing for complete chip
* Manage chip level integration and physical verification Technical Skills required:
Must have Skills:
* MSEE/MSCS/MSCE degree or BSEE/BSCS/BSCE degree
* Experience with advanced technology like 7nm, 5nm in terms of doing large chips physical design
* Expertise developing flow for PD using synopsys/cadence tool chains
* Expertise in signoff (timing, IR, EM, Verification) for tapeout quality GDS
* Guide and manage PD team members * Participate in pre-sales activities
* Work with teams across different locations
Good to have skills: * Scripting tools like Tcl, Shell
Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)
Subscribe to job alerts and upload your resume!
*By registering with our site, you agree to our
Terms and Privacy Policy.